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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1833 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 multichannel, 24-bit, 192 khz, - dac features 5 v stereo audio system with 3.3 v tolerant digital interface supports 96 khz sample rates on six channels and 192 khz on 2 channels supports 16-/20-/24-bit word lengths multibit sigma-delta modulators with perfect differential linearity restoration for reduced idle tones and noise floor data directed scrambling dacsleast sensitive to jitter differential output for optimum performance dacs signal-to-noise and dynamic range: 110 db C94 db thd + n6-channel mode C95 db thd + n2-channel mode on-chip volume control per channel with 1024-step linear scale software controllable clickless mute digital de-emphasis processing supports 256 f s , 512 f s , and 768 f s master clock modes power-down mode plus soft power-down mode flexible serial data port with right-justified, left- justified, i 2 s-compatible and dsp serial port modes supports packed data mode (tdm) for dacs 48-lead lqfp plastic package applications dvd video and audio players home theatre systems automotive audio systems set-top boxes digital audio effects processors functional block diagram agnd dgnd filtr filtd mclk cdata clatch cclk outlp1 outln1 outlp2 outln2 outlp3 outln3 outrp3 outrn3 outrp2 outrn2 outrp1 outrn1 zero flags dvdd1 dvdd2 avdd reset sout AD1833 spi port data port l/ r clk bclk sdin1 sdin2 sdin3 interpolator dac interpolator dac interpolator dac interpolator dac interpolator dac filter engine interpolator dac general description the AD1833 is a complete, high-performance, single- chip, multi- channel, digital audio playback system. it features six audio playback channels each comprising a high-performance digital interpolation filter, a multibit sigma-delta modulator featuring analog devices patented technology and a c ontinuous-time voltage-out analog dac section. other features include an on-chip clickless attenuator and mute capability, per channel, programmed through an spi-compatible serial control p ort. the AD1833 is fully compatible with all known dvd formats, catering for up to 24-bit word lengths at sample rates of 48 khz and 96 khz on all six channels while supporting a 192 khz sample rate on two channels. it also provides the ?edbook standard 50 s/15 s digital de-emphasis filters at sample rates of 32 khz, 44.1 khz, and 48 khz. the AD1833 has a very flexible serial data input port that allows for glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers, and sample rate converters. the AD1833 can be configured in left-justified, i 2 s, right-justified, or dsp serial port compatible modes. the AD1833 accepts serial audio data in msb first, two? complement format. while the AD1833 can be operated from a single 5 v power supply, it also features a separate supply pin for its digital interface which allows the device to be interfaced to devices using 3.3 v power supplies. it is fabricated on a single monolithic integrated circuit and is housed in a 48-lead lqfp package for operation over the tem- perature range ?0 c to +85 c.
rev. 0 C2C AD1833?pecifications test conditions unless otherwise noted supply voltages (av dd , dv dd ) 5.0 v ambient temperature 25 c input clock 12.288 mhz, (256 f s mode) input signal nominally 1 khz, 0 dbfs (full scale) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance 500 pf load impedance 10 k ? notes performance of all channels are identical (exclusive of the interchannel gain mismatch and interchannel phase deviation specifi cations). specifications subject to change without notice. parameter min typ max unit test conditions analog performance digital-to-analog converters dynamic range (20 hz to 20 khz, ?0 dbfs input) with a-weighted filter 106.5 110 db 110.5 db f s = 96 khz total harmonic distortion + noise ?5 ?9 db two channels active ?4 db six channels active ?5 db 96 khz, two channels active ?4 db 96 khz, six channels active snr 110 db interchannel isolation 108 db dc accuracy gain error 3.0 % interchannel gain mismatch 0.2 % gain drift 80 ppm/ c interchannel crosstalk (eiaj method) ?20 db interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (max attenuation) 63.5 db mute attenuation ?20 db de-emphasis gain error 0.1 db full-scale output voltage at each pin (single-ended) 1.0 (2.8) v rms (v p-p) output resistance measured differentially 150 ? common-mode output volts 2.2 v dac interpolation filter?8 khz pass band 20 khz pass band ripple 0.01 db stop band 24 khz stop band attenuation 70 db group delay 510 s dac interpolation filter?6 khz pass band 37.7 khz pass band ripple 0.03 db stop band 55.034 khz stop band attenuation 70 db group delay 160 s dac interpolation filter?92 khz pass band 89.954 khz pass band ripple 1db stop band 104.85 khz stop band attenuation 70 db group delay 140 s
rev. 0 C3C AD1833 parameter min typ max unit test conditions digital i/o input voltage hi 3.0 v input voltage lo 0.8 v output voltage hi dv dd2 0.4 v output voltage lo 0.4 v power supplies supply voltage (av dd and dv dd1 ) 4.5 5.0 5.5 v supply voltage (dv dd2 ) 3.3 dv dd1 v supply current i analog 38.5 42 ma supply current i digital 42 45.5 ma active 2 ma power-down power supply rejection ratio 1 khz 300 mv p-p signal at analog supply pins ?0 db 20 khz 300 mv p-p signal at analog supply pins ?0 db specifications subject to change without notice. absolute maximum ratings * (t a = 25 c unless otherwise noted) av dd , dv ddx to agnd, dgnd . . . . . . . . ?.3 v to +6.5 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital i/o voltage to dgnd . . . . . ?.3 v to dv dd2 + 0.3 v analog i/o voltage to agnd . . . . . . ?.3 v to av dd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1833 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device lqfp, ja thermal impedance . . . . . . . . . . . . . . . . . 91 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. ordering guide model temperature range package description package option AD1833ast ?0 c to +85 c thin plastic quad flatpack st-48 eval-AD1833eb evaluation board pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) outrp1 outrn1 avdd avdd agnd agnd agnd outlp1 outln1 avdd avdd agnd agnd agnd dgnd dvdd1 zeroa zero3r dgnd dvdd2 reset zero1l AD1833 zero3l zero1r outln2 outlp2 outln3 outlp3 avdd filtd filtr agnd outrp3 outrn3 outrp2 outrn2 zero2r clatch cdata cclk l/ r clk bclk mclk sdin1 sdin2 sdin3 sout zero2l
rev. 0 AD1833 C4C mclk input t dmh t dml t pdrp reset input figure 1. mclk and reset timing t dls bclk l/ r clk sdata left-justified mode sdata right-justified mode lsb sdata i 2 s-justified mode t dbh t dbl t dds msb msb-1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 16-bit clocks (16-bit data) figure 2. serial data port timing digital timing (guaranteed over ?0 c to +85 c, av dd = dv dd = 5.0 v 10%) min unit t dml mclk lo pulsewidth (all modes) 15 ns t dmh mclk hi pulsewidth (all modes) 15 ns t dbh bclk hi pulsewidth 15 ns t dbl bclk lo pulsewidth 15 ns t dls lrclk setup 5 ns t dlh lrclk hold (dsp serial port mode only) 10 ns t dds sdata setup 5 ns t ddh sdata hold 15 ns t pdrp pd/rst lo pulsewidth 10 ns t cch cclk hi pulsewidth 10 ns t ccl cclk lo pulsewidth 10 ns t csu cdata setup time 5 ns t chd cdata hold time 10 ns t clh clatch hi pulsewidth 10 ns specifications subject to change without notice.
rev. 0 AD1833 C5C pin function descriptions pin mnemonic in/out description 1 outlp1 o dac 1 left channel positive output. 2 outln1 o dac 1 left channel negative output. 3, 4, 33, 34, 44 avdd analog supply. 5, 6, 7, 30, 31, 32, 41 agnd analog ground. 8, 29 dgnd digital ground. 9 dvdd1 digital supply to core logic. 10 zeroa o flag to indicate zero input on all channels. 11 zero3r o flag to indicate zero input on channel 3 right. 12 zero3l o flag to indicate zero input on channel 3 left. 13 zero2r o flag to indicate zero input on channel 2 right. 14 clatch i latch input for control data (spi port). 15 cdata i serial control data input (spi port). 16 cclk i clock input for control data (spi port). 17 l/ r clk i/o left/right clock for dac data input (fstdm output in tdm mode). 18 bclk i/o bit clock for dac data input ( bclktdm output in tdm mode). 19 mclk i master clock input. 20 sdin1 i data input for channel 1 left/right (data stream input in tdm and packed modes). 21 sdin2 i/o data input for channel 2 left/right (l/ r clk output to auxiliary dac in tdm mode). 22 sdin3 i/o data input for channel 3 left/right (bclk output to auxiliary dac in tdm mode). 23 sout o auxiliary i 2 s output (available in tdm mode). 24 zero2l o flag to indicate zero input on channel 2 left. 25 zero1r o flag to indicate zero input on channel 1 right. 26 zero1l o flag to indicate zero input on channel 1 left. 27 reset i power-down and reset control. 28 dvdd2 power supply to external interface logic. 35 outrn1 o dac 1 right channel negative output. 36 outrp1 o dac 1 right channel positive output. 37 outrn2 o dac 2 right channel negative output. 38 outrp2 o dac 2 right channel positive output. 39 outrn3 o dac 3 right channel negative output. 40 outrp3 o dac 3 right channel positive output. 42 filtr reference/filter capacitor connection. recommend 10 f/100 f decouple to analog ground. 43 filtd filter capacitor connection. recommend 10 f/100 f decouple to analog ground. 45 outlp3 o dac 3 left channel positive output. 46 outln3 o dac 3 left channel negative output. 47 outlp2 o dac 2 left channel positive output. 48 outln2 o dac 2 left channel negative output. d15 d14 d0 t chd t cch t csu t ccl cdata cclk clatch t clh figure 3. spi timing
rev. 0 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.008 0.006 0.004 0.002 0 ?.002 ?.004 ?.006 ?.008 ?.01 db hz 10 4 tpc 1. pass band response, 8 mode 10 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 0 10 20 30 db hz 10 4 40 50 60 70 80 90 100 tpc 2. transition band response, 8 mode 0 0.5 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 140 160 db hz 10 5 1.0 tpc 3. complete response, 8 mode 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.1 db hz 10 4 tpc 4. pass band response, 4 mode 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 db hz 10 4 tpc 5. 40 khz pass band response, 4 mode 10 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 0 10 20 30 db hz 10 4 40 50 60 70 80 90 100 tpc 6. transition band response, 4 mode AD1833 typical performance characteristics C6C
rev. 0 AD1833 C7C 0 0.5 1.5 2.0 0 20 40 60 80 100 120 140 160 db hz 10 5 1.0 2.5 3.0 tpc 7. complete response, 4 mode 2.0 012345678 1.5 0.5 0 0.5 1.0 1.5 2.0 db hz 10 4 1.0 tpc 8. 80 khz pass band response, 2 mode 10 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0 10 20 30 db hz 10 5 40 50 60 70 80 90 100 -/*7 -
1 # mode 0 0.5 1.5 2.0 0 20 40 60 80 100 120 140 160 db hz 10 5 1.0 -/*( * # mode
rev. 0 AD1833 C8C functional description device architecture the AD1833 is a 6-channel audio dac featuring multibit sigma-delta ( - ? ) technology. the AD1833 features three stereo converters (giving six channels) where each stereo channel is controlled by a common bit-clock (bclk) and synchroniza- tion signal (l/ r clk). interpolator the interpolator consists of up to three stages of sample rate doubling and half-band filtering followed by a 16 sample zero order hold. the sample rate doubling is achieved by zero stuff- ing the input samples, and a digital half band filter is then used to remove any images above the band of interest and to bring the zero samples to their correct values. by selecting different input sample rates, one, two, or all three stages of doubling may be switched in. this allows for three different sample rate inputs. all three doubling stages are used with the 48 khz input sample rate, with the 96 khz input sample rate only two doubling stages are used, and with the 192 khz input sample rate only one doubling stage is used. in each case the input sample frequency is increased to 384 khz. the zero- order hold (zoh) holds the interpolator samples for upsampling by the modulator. this is done at a rate 16 times the interpola- tor output sample rate. modulator the modulator is a 6-bit, second-order implementation and uses data scrambling techniques to achieve perfect linearity. the modulator samples the output of the interpolator stage(s) at a rate of 6.144 mhz. operating features spi register definitions the spi port allows flexible control of the devices?program- mable functions. it is organized around nine registers; six individual channel volume registers and three control registers. each write operation to the AD1833 spi control port requires 16 bits of serial data in msb-first format. the four most significant b its are used to select one of nine registers (seven register addres ses are reserved), and the bottom 10 bits are then written to that reg ister. this allows a write to one of the nine registers in a single 16-bit transaction. the spi cclk signal is used to clock in the data. the incoming data should change on the falling edge of this signal and remain valid during the rising edge. at the end of the 16 cclk periods, the clatch signal should rise to latch the data internally into the AD1833. see figure 2. the serial interface format used on the control port utilizes a 16-bit serial word as shown in table i. the 16-bit word is divided into several fields: bits 15?2 define the register address, bits 11 and 10 are reserved and must be programmed to 0, and bits 9? are the data field (which has specific definitions, depending on the register selected). table i. control port map register address reserved 1 data field 15 2 14131211109876543210 notes 1 must be programmed to zero. 2 bit 15 = msb bit 15 bit 14 bit 13 bit 12 register function 0 0 0 0 dac control i 0 0 0 1 dac control ii 0 0 1 0 dac volume 1 0 0 1 1 dac volume 2 0 1 0 0 dac volume 3 0 1 0 1 dac volume 4 0 1 1 0 dac volume 5 0 1 1 1 dac volume 6 1 0 0 0 dac control iii 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved
rev. 0 AD1833 C9C dac control register i de-emphasis the AD1833 has a built-in de-emphasis filter that can be used to decode cds that have been encoded with the standard ?ed book?50 s/15 s emphasis response curve. three curves are available; one each for 32 khz, 44.1 khz, and 48 khz sam- pling rates. the filters may be selected by writing to control bits 9 and 8 in dac control register i, see table iii. table iii. de-emphasis settings bit 9 bit 8 de-emphasis 0 0 disabled 0 1 44.1 khz 1 0 32 khz 1 1 48 khz data serial interface mode the AD1833? serial data interface is designed to accept data in a wide range of popular formats including i 2 s, right justified (rj), left justified (lj) and flexible dsp modes. the l/ r clk pin acts as the word clock (or frame sync) to indicate sample interval boundaries. the bclk defines the serial data rate while the data is input on the sdin1-3 pins. the serial mode settings may be selected by writing to control bits 7 through 5 in dac control register i, see table iv. table iv. data serial interface mode settings bit 7 bit 6 bit 5 serial mode 00 0 i 2 s 0 0 1 right justify 0 1 0 dsp 0 1 1 left justify 1 0 0 packed mode 1 (256) 1 0 1 packed mode 2 (128) 1 1 0 aux mode 1 1 1 reserved dac word width the AD1833 will accept input data in three separate word- lengths?6, 20, and 24 bits. the word-length may be selected by writing to control bits 4 and 3 in dac control register i, see table v. table v. word length settings bit 4 bit 3 word length 0 0 24 bits 0 1 20 bits 1 0 16 bits 1 1 reserved power-down control the AD1833 can be powered down by writing to control bit 2 in dac control register i, see table vi. the power-down/ reset bit is not latched when the clatch is brought high to latch the entire word, but only after the following low-to-high clatch transit ion. therefore, to put the part in power-down, or to bring it back up from power-down, the command should be written twice. table vi. power-down control bit 2 power-down setting 0 normal operation 1 power-down mode interpolator mode the AD1833? dac interpolators can be operated in one of three modes? , 4 , or 2 corresponding with 48 khz, 96 khz, and 192 khz modes respectively. the interpolator mode may be selected by writing to control bits 1 and 0 in dac control register i, see table vii. table vii. interpolator mode settings bit 1 bit 0 interpolator mode 00 8 (48 khz) 01 2 (192 khz) 10 4 (96 khz) 1 1 reserved table ii. dac control i function data word power-down interpolator address reserved * de-emphasis serial mode width reset mode 15?2 11 10 9? 7? 4? 2 1? 0000 0 0 00 = none 000 = i 2 s 00 = 24 bits 0 = normal 00 = 8 (48 khz) 01 = 44.1 khz 001 = rj 01 = 20 bits 1 = pwrdwn 01 = 2 (192 khz) 10 = 32.0 khz 010 = dsp 10 = 16 bits 10 = 4 (96 khz) 11 = 48.0 khz 011 = lj 11 = reserved 11 = reserved 100 = pack mode 1 (256) 101 = pack mode 2 (128) 110 = aux mode 111 = reserved * must be programmed to zero.
rev. 0 AD1833 C10C table viii. dac control ii function address reserved * reserved * mute control 15?2 11 10 9? 5 4 3 2 1 0 0001 0 0 0 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 0 = mute off 0 = mute off 0 = mute off 0 = mute off 0 = mute off 0 = mute off 1 = mute on 1 = mute on 1 = mute on 1 = mute on 1 = mute on 1 = mute on * must be programmed to zero. dac control register ii dac control register ii contains individual channel mute controls for each of the 6 dacs. default operation (bit = 0) is muting off. bits 9 through 6 of control register ii are reserved and should be programmed to zero, see table viii. table ix. muting control bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 muting xxxxx1 m ute channel 1 xxxx1 x m ute channel 2 xxx1 xx m ute channel 3 x x 1 x x x mute channel 4 x1 xxxx m ute channel 5 1 xxxxx m ute channel 6 dac control register iii stereo replicate the AD1833 allows the stereo information on channel 1 (sdin1?eft 1 and right 1) to be copied to channels 2 and 3 (left/right 2 and left/right 3). these signals can be used in an external summing amplifier to increase potential signal snr. stereo r eplicate mode can be enabled by writing to control bit 5, see table xi. note that replication is not reflected in the zero flag status. table xi. stereo replicate bit 5 stereo mode 0 normal 1 channel 1 data replicated on channels 2 and 3 table x. dac control iii function stereo replicate address reserved * reserved * (192 khz) mclk select zero detect reserved 15?2 11 10 9? 5 4? 2 1? 1000 0 0 0 0 = normal 00 = 256 f s (mclk 2) 0 = active high 1 = replicate 01 = 512 f s (mclk 1 = active low straight through) 10 = 768 f s (mclk 2/3) * must be programmed to zero.
rev. 0 AD1833 C11C mclk select the AD1833 allows the matching of available external mclk frequencies to the required sample rate. the oversampling rate can be selected from 256 f s , 512 f s or 768 f s by writing to bit 4 and bit 3. internally the AD1833 requires an mclk of 512 f s ; therefore, in the case of 256 f s mode, a clock doubler is used, whereas in 768 f s mode, a divide-by-3 block (/3) is first implemented, followed by a clock doubler. see table xii. table xii. mclk settings bit 4 bit 3 oversample ratio 0 0 256 f s (mclk 2 internally) 0 1 512 f s 1 0 768 f s (mclk 2/3 internally) 1 1 reserved channel zero status the AD1833 provides individual logic output status indicators when zero data is sent to a channel for 1024 or more consecutive sample periods. there is also a global zero flag that indicates all channels contain zero data. the polarity of the active zero signal table xiv. mclk vs. sample rate selection mclk (mhz) sampling rate f s (khz) interpolator mode 256 f s 512 f s 768 f s 32 8 (normal) 64 4 (double) 8.192 16.384 24.576 128 2 (4 times) 44.1 8 (normal) 88.2 4 (double) 11.2896 22.5792 33.8688 176.4 2 (4 times) 48 8 (normal) 96 4 (double) 12.288 24.576 36.864 192 2 (4 times) table xv. volume control registers address reserved * volume control 15?2 11 10 9? 0 0 1 0 0 0 channel 1 volume control (outl1) 0 0 1 1 channel 2 volume control (outr1) 0 1 0 0 channel 3 volume control (outl2) 0 1 0 1 channel 4 volume control (outr2) 0 1 1 0 channel 5 volume control (outl3) 0 1 1 1 channel 6 volume control (outr3) * must be programmed to zero. is programmable by writing to control bit 2, see table xiii. the six individual channel flags are best used as three stereo zero flags by combining pairs of them through suitable logic gates. then, w hen both the left and right input are zero for 1024 clock cycles, i.e., a stereo zero input for 1024 sample periods, the combined r esult of the two individual flags will go active indicating a stereo zero. table xiii. zero detect bit 2 channel zero status 0 active high 1 active low dac volume control registers the AD1833 has six volume control registers, one each for the six dac channels. volume control is exercised by writing to the relevant register associated with each dac. this setting is used to attenuate the dac output. full-scale setting (all 1s) is equiva- lent to zero attenuation. see table xv.
rev. 0 AD1833 C12C i 2 s timing i 2 s timing uses an l/ r clk to define when the data being trans- mitted is for the left channel and when it is for the right channel. the l/ r clk is low for the left channel and high for the right channel. a bit clock running at 64 f s is used to clock in the data. there is a delay of one bit clock from the time the l/ r clk signal changes state to the first bit of data on the sdinx lines. the data is written msb first and is valid on the rising edge of bit clock. left justified timing left justified (lj) timing uses an l/ r clk to define when the data being transmitted is for the left channel and when it is for the right channel. the l/ r clk is high for the left channel and low for the right channel. a bit clock running at 64 f s is used to clock in the data. the first bit of data appears on the sdinx lines at the same time the l/ r clk toggles. the data is written msb first and is valid on the rising edge of bit clock. right justified timing right justified (rj) timing uses an l/ r clk to define when the data being transmitted is for the left channel and when it is for the right channel. the l/ r clk is high for the left channel and low for the right channel. a bit clock running at 64 f s is used to clock in the data. the first bit of data appears on the sdinx 8-bit clock periods (for 24-bit data) after l/ r clk toggles. in rj mode the lsb of data is always clocked by the last bit clock before l/ r clk transitions. the data is written msb first and is valid on the rising edge of bit clock. left channel right channel lsb +1 lsb msb l/ r clk input bclk input sdata input lsb +2 msb 2 msb 1 msb lsb +1 lsb lsb +2 msb 2 msb 1 msb figure 4. i 2 s timing diagram left channel right channel lsb +1 lsb l/ r clk input bclk input sdata input lsb +2 msb 2 msb 1 msb lsb +1 lsb lsb +2 msb 2 msb 1 msb msb 1 msb figure 5. left-justified timing diagram left channel right channel lsb +1 lsb l/ r clk input bclk input sdata input lsb +2 msb 2 msb 1 lsb msb lsb +1 lsb lsb +2 msb 2 msb 1 msb figure 6. right-justified timing diagram
rev. 0 AD1833 C13C aux-mode timing?nterfacing to a sharc in aux mode, the AD1833 is the master and generates a frame sync signal (fstdm) on its l/ r clk pin, and a bit clock (bclktdm) on its bclk pin, both of which are used to control the data transmission from the sharc. the bit clock runs at a frequency of 256 f s. in this mode all data is writ- ten on the rising edge of the bit clock and read on the falling edge of the bit clock. the AD1833 starts the frame by raising a frame sync on the rising edge of bit clock. the sharc recog- nizes this on the following falling edge of bit clock, and is ready to start outputting data on the next rising edge of bit clock. each channel is given a 32-bit clock slot, the data is left justified and uses 16, 20, or 24 of the 32 bits. an enlarged dia- gram (see figure 6) is provided detailing this. the data is sent from the sharc to the AD1833 on the sdin1 pin and is provided in the following order, msb first?nternal dacl0, internal dacl1, internal dacl2, aux dacl0, internal dacr0, internal dacr1, internal dacr2 and aux dacr0. the data is written on the rising edge of bit clock and read by the AD1833 on the falling edge of bit clock. the left and right data destined for the auxiliary dac is sent to it in standard i 2 s format in the next frame using the sdin2, sdin3, and sout pins as the l/ r clk, bclk, and sdin pins respec- tively for comm unicating with the auxiliary dac. dsp mode timing dsp mode timing uses the rising edge of the frame sync signal on the l/ r clk pin to denote the start of the transmis- sion of a data word. note that for both left and right channels a rising edge is used; therefore in this mode there is no way to determine which data is intended for the left channel and which is intended for the right. the dsp writes data on the rising edge of bclk and the AD1833 reads it on the falling edge. the dsp raises the frame sync signal on the rising edge of bclk and then proceeds to transmit data, msb first, on the next rising edge of bclk. the data length can be 16, 20, or 24 bits. the frame sync signal can be brought low any time at or after the msb is transmitted, but must be brought low at least one bclk period before the start of the next channel transmission. internal dac l0 internal dac l1 internal dac l2 auxiliary dac l0 internal dac r0 internal dac r1 internal dac r2 auxiliary dac r0 fstdm bclktdm msb 24-bit data 20-bit data 16-bit data bclktdm msb 1 msb 2 msb 3 msb 4 lsb +8 lsb +7 lsb +6 lsb +5 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb 1 msb 2 msb 3 msb 4 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb 1 msb 2 msb 3 msb 4 lsb figure 7. aux-mode timing l/ r clk bclk sdata msb msb 1 msb 2 msb 3 msb 4 msb 5 msb 6 msb msb 1 msb 2 msb 3 msb 4 msb 5 msb 6 msb 32 bclks 32 bclks figure 8. dsp mode timing sharc is a registered trademark of analog devices, inc.
rev. 0 AD1833 C14C packed mode 128 in packed mode 128, all six data channels are ?acked?into one sample interval on one data pin. the bclk runs at 128 f s ; therefore there are 128 bclk periods in each sample inter- val. each sample interval is broken into eight time slots, six slots of 20 bclks and two of four bclks. the data length is restricted in this mode to a maximum of 20 bits. the three left channels are written first, msb first, and the data is written on the falling edge of bclk. after the three left channels are written, there is a space of four bclks and then the three right channels are written. the l/ r clk defines the left and right data tr ansmis- sion; it is high for the three left channels and low for the three right channels. packed mode 256 in packed mode 256 all six data channels are ?acked?into one sample interval on one data pin. the bclk runs at 256 f s ; therefore there are 256 bclk periods in each sample interval. each sample interval is broken into eight time slots of 32 bclks each. the data length can be 16, 20, or 24 bits. the three left channels are written first, msb first, and the data is written on the falling edge of bclk with a one bclk period delay from the start of the slot. after the three left channels are written, there is a space of 32 bclks and then the three right channels are written. the l/ r clk defines the left and right data trans- mission; it is low for the three left channels and high for the three right channels. slot 1 left 0 slot 2 left 1 slot 3 left 2 slot 4 right 0 slot 5 right 1 slot 6 right 2 l/ r clk bclk data msb 24-bit data 20-bit data 16-bit data bclk msb 1 msb 2 msb 3 msb 4 lsb +8 lsb +7 lsb +6 lsb +5 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb 1 msb 2 msb 3 msb 4 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb 1 msb 2 msb 3 msb 4 lsb figure 10. packed mode 256 slot 1 left 0 slot 2 left 1 slot 3 left 2 blank slot 4 sclks slot 4 right 0 slot 5 right 1 slot 6 right 2 blank slot 4 sclks msb 20-bit data 16-bit data bclk msb 1 msb 2 msb 3 msb 4 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb 1 msb 2 msb 3 msb 4 lsb bclk data l/ r clk figure 9. packed mode 128
rev. 0 AD1833 C15C 2.80k 560pf npo 5.62k 150pf npo 5.62k v out 5.62k v out+ 560pf npo 2.80k 5.62k 150pf npo op275 604 49.9k 2.2nf npo vfilt out 5 6 7 figure 11. suggested output filter schematic 2 4 6 8 10 12 14 16 0 20 40 60 80 100 120 140 18 20 khz dbr 0 figure 12. dynamic range for 1 khz @ C60 dbfs, 110 db, triangular dithered input 2 4 6 8 10 12 14 16 0 20 40 60 80 100 120 140 18 20 khz dbr 0 figure 13. input 0 dbfs @ 1 khz, bw 20 hz to 20 khz, sr 48 khz, thd + n C95 dbfs 20 40 60 80 0 20 40 60 80 100 120 140 100 120 khz dbr 0 '
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rev. 0 AD1833 C16C 90 80 70 60 70 80 90 100 50 40 dbfs dbr 100 30 20 10 0 60 110 120 figure 17. thd + n ratio vs. amplitude, input 1 khz, sr 48 khz, 24-bit 90 80 70 60 30 40 50 60 70 80 90 50 40 dbfs dbr 100 100 30 20 10 0 20 110 120 figure 18. thd + n ratio vs. amplitude, @ 1 khz, sr 48 khz
rev. 0 AD1833 C17C clatch cdata cclk l/ r clk bclk sdin1 sdin2 sdin3 sout mclk outlp1 outln1 outlp2 outln2 outlp3 outln3 outrp1 outrn1 outrp2 outrn2 outrp3 outrn3 vrefx filtdac dgnd1 dgnd2 gnd dvdd1 dvdd2 avdd1 avdd2 avdd avdd avdd AD1833 0.1 f + + + 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f avdd 5v 5v dvdd intf + + 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f + + clatch cdata cclk l1+ l1 l2+ l2 l3+ l3 r1+ r1 r2+ r2 r3+ r3 1 2 47 48 45 46 36 35 38 37 40 39 42 43 14 15 16 17 18 20 21 22 23 19 9 28 33 3 34 44 4 29 8 41 32 5 31 6 30 7 gnd gnd gnd gnd gnd gnd + 10 f 0.1 f + 10 f rxp rxn filt agnd dgnd sdata fsync sck mck m0 m1 m2 m3 c u cbl verf erf co/eo ca/e1 cb/e2 cc/f0 cd/f1 ce/f2 sel cs12/fck dir-cs8414 shld1 shld1 shld1 shld1 dvdd out u5 torx173 10nf 10nf 47nf 1k 75ro 5v 10k 0.1 f l5 0.1 f 10 f 26 11 12 19 23 24 18 17 1 14 15 28 25 6 5 4 3 2 27 16 13 8 21 20 10 9 22 va+ vd+ 7 5 3 6 2 4 1 pal dvdd avdd figure 19. example digital interface
rev. 0 AD1833 C18C 48-lead thin plastic quad flatpack (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm).
C19C
C20C c02336C2.5C4/01(0) printed in u.s.a.

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